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User Guide Status to Version 3.5 Dt:21.05.2021 in progress

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Act Title EN FR DE PT RU EL ES IT NL
Logisim References
3.5 About the program __ __ _M _T _T
3.5 GNU General Public License v3 __ X X X X
3.5 GNU General Public License v3, translated X __ __ *T __
3.5 The Logisim-evolution user’s Guide __ __ __ __ __
3.5 Beginner's tutorial __ __ __ __ __
3.5 Step 0: Orienting yourself __ __ __ __ __
3.5 Step 1: Adding gates __ __ __ __ __
3.5 Step 2: Adding wires __ __ __ __ __
3.5 Step 3: Adding text __ __ _M __ _M
3.5 Step 4: Testing your circuit __ __ __ __ __
3.5 Step 5: The step by step mode _V __ _M _M _M
3.2 The graphical interface __ __ __ _V _V
3.2 The canvas _V __ _T _T _M
3.3 The menus _V __ _M _T _M
3.3 The explorer pane _V __ _V _V _V
3.3 The tools bars _V __ _T _T _T
3.2 The attribute table __ __ __ __ __
3.2 Attributes of tools and components __ __ __ __ __
3.2 Subcircuits __ __ _M _V _V
3.2 Creating circuits __ __ _M _V _V
3.2 Using subcircuits _V __ _M _V _V
3.2 Selecting the appearance of a subcircuit _V __ _M _M _M
3.3 Personalise appearance _V __ _M _M _M
3.2 Debugging subcircuits __ __ _M _V _V
3.2 Logisim libraries __ __ _M __ __
3.2 Additional features _V __ _V _V _V
3.2 Creating bundles __ __ __ __ __
3.2 Splitters __ __ _V _V _V
3.2 Wire colors _V __ _M _V _V
3.2 Self-numbered labels _V __ _M _M _M
3.2 Placing components in a matrix _V __ _M _M _M
3.3 Combinational analysis _V __ __ __ __
3.3 Opening Combinational Analysis __ __ __ __ __
3.3 Editing the truth table _V __ _M _M _M
3.3 Creating expressions __ __ _M _M _M
3.3 Generating a circuit __ __ _V _V _V
3.2 Menu reference __ __ _M __ __
3.2 The File menu _V __ _V _V _V
3.2 The Edit menu _V __ _V _V _V
3.2 The Project menu __ __ _M __ __
3.2 The Simulate menu V __ _M _V _V
FPGA Menu
3.2 The Window and Help menus __ __ _M __ __
3.2 Export tab _V __ _V _V _V
3.2 Printing tab _V __ _V _V _V
3.3 Memory components _V __ __ __ __
3.3 Poking memory _V __ _M _M _M
3.3 Hex editor _V __ __ _V _V
3.3 Pop-up menus and files _V __ _V _V _V
3.3 Memory file panel _V __ __ __ __
3.3 v2.0 raw _V __ __ __ __
3.3 v3.0 hex words _V __ __ __ __
3.3 v3.0 hex bytes _V __ __ __ __
3.3 Binary data _V __ __ __ __
3.3 Ascii byte _V __ __ __ __
3.4 Chronograms _V __ __ __ __
3.4 The Selection tab _V __ __ __ __
3.4 The Timetable windows _V __ __ __ __
2.7 Chronograms _V __ __ __ __
2.7 The Selection tab _V __ __ __ __
2.7 The Timetable windows _V __ __ __ __
The Table tab X X X X X
The File tab X X X X X
The Test Vector windows _* _* _* _* _*
2.7 Command-line verification __ __ _T __ __
2.7 Substituting libraries __ __ _T __ __
2.7 Other verification options __ __ _T __ __
2.7 Tes¨ting multiple files __ __ _T __ __
2.7 The Test Vector windows _V __ _T _T _T
3.3 Application preferences CV C_ _T C_ C_
3.3 The Template tab __ __ _T __ __
3.3 The International tab __ __ _T __ __
3.5 The Window tab CV C_ _T CV CV
3.5 The Layout tab C_ C_ _T CT CT
3.5 The Simulation tab
3.5 The Experimental tab __ __ _T __ __
3.5 The Sofware tab
3.5 The FPGA tab
3.3 The command line __ __ _V _V _V
3.3 Project options __ __ _T __ __
3.3 The Simulation tab _V __ _T _V _V
3.3 The Toolbar tab __ __ _T __ __
3.3 The Mouse tab __ __ _T _V _V
3.2 Value propagation _V __ _M __ __
3.2 Gate delays __ __ _M __ __
3.2 Oscillation errors __ __ _M __ __
3.2 Shortcomings __ __ _M __ __
JAR libraries __ __ __ __ __
Gray Code Incrementer __ _T __ __ __
Library Class __ _T __ __ __
Simple Gray Code Counter __ _T __ __ __
Gray Code Counter __ _T __ __ __
Guidelines __ _T __ __ __